1. Field of the Invention
The present invention relates to a bidirectional thyristor device which can be used in a commercial AC power source line or the like, and particularly to a structure of a chip of a bidirectional photothyristor to which a trigger signal can be given in response to light irradiation.
2. Description of the Related Art
Conventionally, a bidirectional photothyristor 2 which, as shown in FIGS. 9 to 11, is formed on a single semiconductor chip such as an N type silicon substrate 1 and which is optically controlled by giving a gate trigger signal in response to light irradiation is widely used as a so-called solid state relay (hereinafter, often abbreviated as "SSR"). FIG. 9 is a schematic plan section view, FIG. 10 is a section view taken along a section line X--X of FIG. 9, and FIG. 11 is a diagram of an equivalent circuit of the bidirectional photothyristor 2. FIG. 9 corresponds to a section view taken along a section line IX--IX of FIG. 10.
Usually, the N type silicon substrate 1 has an impurity concentration of 10.sup.13 to 10.sup.15 cm.sup.-3. A channel stopper region 6 is disposed around a portion where the bidirectional photothyristor 2 is formed. An N type diffusion layer 7 is disposed on a back of the N type silicon substrate 1. The channel stopper region 6 and the N type diffusion layer 7 are formed by diffusing N type impurities in a higher concentration than that of the N type silicon substrate 1. An A1 conductor 8 is formed on a surface of the N type silicon substrate 1 in order to attain electrical connections. A SiO.sub.2 (silicon oxide) film 9 is formed in a portion where electrical insulation is required. An oxygen-doped semi-insulating film 10 is formed on the SiO.sub.2 film.
In the bidirectional photothyristor 2, P-gate light receiving portions 11 and 21 are formed in order to receive a light signal. In each of the portions, the A1 conductor 8 is removed so as to form an opening. P type anode diffusion regions 12 and 22, and P type P-gate diffusion regions 13 and 23 which are opposed to the anode diffusion regions 12 and 22 are disposed on the surface of the N type silicon substrate 1. The P-gate light receiving portions 11 and 21 are disposed on the P-gate diffusion regions 13 and 23, respectively. N type cathode diffusion regions 14 and 24 are formed in the P-gate diffusion regions 13 and 23, respectively. Gate resistance regions 15 and 25 are formed between the P-gate diffusion regions 13 and 23, and anode diffusion regions 22 and 12 which are disposed at a distance L from the P-gate diffusion regions 13 and 23, respectively. In this way, the P type anode diffusion regions 12 and 22, the N type silicon substrate 1, the P type P-gate diffusion regions 13 and 23, and the N type cathode diffusion regions 14 and 24 form PNPN type lateral reverse blocking thyristors 16 and 26 having the gate resistance regions 15 and 25, respectively. In the bidirectional photothyristor 2, the reverse blocking thyristors 16 and 26 are connected to each other in a reverse direction so as to be formed as channels ch1 and ch2, respectively. When a surface of the bidirectional photothyristor 2 is directly irradiated with light, the thyristor functions as a fundamental optically controlled bidirectional thyristor. When an AC power source is to be controlled, the thyristor may be provided with a zero-cross function in which a trigger is enabled only in a restricted voltage range in a vicinity of a zero-cross point of the AC power source.
As described above, the impurity concentration of the N type silicon substrate 1 is 10.sup.13 to 10.sup.15 cm.sup.-3. The P type diffusion regions, such as the anode diffusion regions 12 and 22 and the P-gate diffusion regions 13 and 23, use boron (B) or the like as impurities and their impurity concentrations are 10.sup.15 to 10.sup.19 cm.sup.-3. The N type diffusion regions, such as the cathode diffusion regions 14 and 24, use phosphorus (P) or the like as impurities and their impurity concentrations are set to be 10.sup.19 cm.sup.-3 or higher. The distance L between the anode diffusion regions 12, 22 and the P-gate diffusion regions 13, 23 is about 15 to 30 .mu.m.
The anode diffusion region 12 of the one thyristor 16, and the cathode diffusion region 24 of the other photothyristor 26 are electrically led out to the surface of the N type silicon substrate 1 via the A1 conductor 8 and then connected as an electrode T1 in parallel by wires to a frame terminal which is disposed on a package housing the bidirectional photothyristor 2. Similarly, the cathode diffusion region 14 of the one thyristor 16, and the cathode diffusion region 24 of the other photothyristor 26 are electrically connected by wires to an electrode T2. The SiO.sub.2 film 9 and the oxygen-doped semi-insulating film 10 are used as passivation films.
As shown in FIG. 11, in the thyristors 16 and 26, PNP transistors 17 and 27, and NPN transistors 18 and 28 are equivalently formed. Junction capacitances Co are parasitically formed between the bases and the collectors of the PNP transistors 17, 27 and the NPN transistors 18, 28.
The thus configured lateral bidirectional photothyristor 2 is requested to enhance the light sensitivity, and also to improve noise immunity so that ignition does not occur erroneously by a noise. For example, Japanese Examined Patent Publication JP-B2 3-37746 (1991) discloses a technique which can prevent a malfunction due to a sharp noise and improve the light sensitivity, without using complex production steps.
In the prior art technique, in order to design a thyristor so as to give more advantages to both the chip sensitivity and the noise resistance which are in a tradeoff relationship, h.sub.FE of each lateral PNP transistor is increased so as to improve the light sensitivity, and the gate resistance is lowered so as to enhance the noise resistance. Moreover, a phosphorus diffusion layer is formed on a back of a semiconductor substrate so that h.sub.FE of each PNP transistor is further increased.
Regarding the noise resistance of a thyristor, a thesis entitled "Analysis on the dV/dt characteristics of a lateral PNPN device" is printed in SSD 78-14, pp. 7 to 16. According to the thesis, the dV/dt characteristics of a thyristor device have been analyzed by using an enhanced Ebers-Moll model, and it has been successful to grasp the dependency of the dV/dt characteristics on the device constants. It has been found that parameters which largely affect the dV/dt characteristics are a gate-cathode resistance R.sub.Gk, a base width of PNP transistor, and a gate junction area. Also it has been found that h.sub.FE of the NPN transistor and the cathode area exert relatively small effects.
As shown in FIG. 11, a line of a commercial AC power source (hereinafter, often abbreviated as "AC") is connected to external frame terminals T1 and T2 of the bidirectional photothyristor 2. In this case, when a pulse-like noise voltage whose peak value reaches about 2,000 V on a steep rising edge of a pulse is superimposed on the AC line, there occurs a malfunction where erroneous ignition is caused even in the absence of light irradiation. It is considered that this is caused by the following reason. First, a displacement current i.sub.D indicated by a first expression below flows through the junction capacitances Co shown in FIG. 11 and enters the P-gate diffusion regions 13 and 23 to function as a trigger current, thereby causing the malfunction. Hereinafter, such a mode is referred to as a dV/dt mode. ##EQU1##
When it is assumed that Co is constant, the first expression is modified as the following second expression. ##EQU2##
As a result, it will be seen that, as the value of dV/dt is larger, the displacement current i.sub.D is increased and erroneous ignition occurs more easily. In other words, from the second expression, the gate voltage V.sub.G of each of the thyristors 16 and 26 is indicated by the following third expression. ##EQU3## When a value of the gate voltage V.sub.G exceeds an active voltage V.sub.GK of the corresponding thyristor 16 or 26, erroneous ignition occurs.
In a second mode in which erroneous ignition is caused by a noise, a pulse-like noise voltage falls to be turned off, a characteristic voltage is then generated at the P gate with a delay of several tens of microseconds, and this voltage functions as to generate a trigger current, thereby causing a malfunction. This mode is referred to as a delay voltage mode.
FIGS. 12 to 14 show an assumed cause of a malfunction due to the delay voltage mode, and a related configuration. As shown in FIG. 12, a positive voltage is applied to the anode diffusion region 12 of the one thyristor 16 as an anode A, and the cathode diffusion region 14 is grounded as a cathode electrode K. As a result, the anode diffusion region 22 of the other photothyristor 26 is grounded so as to produce a reversely biased state. An electrical resistance of the N type silicon substrate 1 between the one anode diffusion region 12 and the P-gate diffusion region 13 is equivalently indicated as R1, and an equivalent resistance of the N type silicon substrate 1 between the one anode diffusion region 12 and the other anode diffusion region 22 is indicated as R2. The junction capacitances between the N type silicon substrate 1, and the P type anode diffusion region 12, the P-gate diffusion region 13, the anode diffusion region 22 are indicated by C1, C2, and C4, respectively. The junction capacitance between the P-gate diffusion region 13 and the cathode diffusion region 14 is indicated as C3. A gate resistance formed in the gate resistance region 15 is indicated as R.sub.GK. As shown in FIG. 13, it will be seen that an equivalent differentiation circuit is parasitically formed. When an input voltage Vin on which a noise pulse with a peak value of 2,000 V (max) is superimposed is applied to an input side of the circuit, in an output voltage Vout appearing at the P gate P.sub.G which is formed in the P-gate diffusion region 13, differential outputs corresponding to rise and fall of the noise pulse, and a delay voltage in which certain time has elapsed after the fall are generated as shown in FIG. 14. An upper portion of FIG. 14 shows a change V1 (V) of the input voltage Vin of FIG. 13. When a noise with a pulse width of 1 .mu.s and a peak value of 2,000 V is input between a time t=0 and a time t=1, in V2 (V) of the output voltage Vout, differential waveforms corresponding to the rise and the fall are output at time t=0 and time t=1, respectively, and a delay voltage is generated near and after a time t=15 as shown in a lower portion of FIG. 14.
In order to improve the noise resistance in the dV/dt mode, usually, methods such as that the junction capacitances Co of the P-gate diffusion regions 13 and 23 are reduced and the gate resistance R.sub.GK or the current amplification factors h.sub.FE of the NPN transistors 18 and 28 are suppressed are employed. However, the reduction of the junction capacitances Co of the P-gate diffusion regions 13 and 23 causes the light receiving regions of the P-gate light receiving portions 11 and 21 to be narrowed, and the reduction of the gate resistance R.sub.GK and the current amplification factors h.sub.FE of the NPN transistors causes the light sensitivity of the photothyristor to be lowered. In other words, there is so-called tradeoff relationship between the noise resistance and the light sensitivity, and improvement of one of them involves impairment of the other. The above-mentioned prior art technique of Japanese Examined Patent Publication JP-B2 3-37746 (1991) discloses a configuration for improving both the noise resistance and the light sensitivity.
Recently, an SSR is requested to reduce the power consumption or to be directly driven by a microcomputer. Furthermore, it is strongly requested to enhance the sensitivity. The most important problem is to attain both a high sensitivity in a range where a minimum input trigger current I.sub.FT is about 5 mA, and a high noise resistance conflicting therewith, and also to attain cost reduction including reduction in an area of a semiconductor chip. There is no literature or the like which points out or elucidates a phenomenon of the delay voltage mode which causes a malfunction due to a noise, and no effective countermeasure against the phenomenon is taken.